Static random access memories designed as integrated circuits require increasingly short access times to stay commercially competitive. One method that has been used to decrease access times has been address transition detection, or ATD. (See, for example, Gubbels, W. et al., "A 40-ns/100-pF Low Power Full-CMOS 256K (32K.times.8) SRAM," IEEE Journal of Solid-State Circuits, vol. 22, no. 5, Oct. 1987; Matsui, M. "A 25-ns 1-Mbit CMOS SRAM with Loading-Free Bit Lines," IEEE Journal of Solid-State Circuits, vol. 22, no. 5, Oct. 1987; Wang, K. et al., "A 21-ns 32K.times.8 CMOS Static RAM with a Selectively Pumped p-Well Array," IEEE Journal of Solid-State Circuits, vol. 22, no. 5, Oct. 1987.) ATD allows a memory access to begin as soon as a change in an address is detected. ATD is especially useful in improving memory access time in a memory with long bit lines. With short bit lines, however, ATD no longer provides a speed advantage.
An ATD memory access comprises the stages of equalization, word line driving, bit line driving, data line sensing, and outputting. A built-in limitation of ATD is that it contains the equalization stage, in which nodes must be precharged before the access begins. In order to further speed up static random access memories, a new technique not relying on ATD's equalization stage and minimizing the time from a valid address to a valid word line is needed. Merely eliminating ATD and the equalization stage creates a problem, however. The problem is that amplifiers work well with ATD by providing a high voltage gain and a large differential output signal, but that the data line amplifiers are relatively slow when ATD is not used. An improvement in access time of the memory would be realized if the equalization of the ATD method could be eliminated while retaining rapid sensing and output signal development, a scenario in which only the stages of word line driving, bit line driving, sensing, and outputting remain.